This application claims the priority benefit of Taiwan application serial no. 88123395, filed Dec. 31, 1999.
1. Field of the Invention
The present invention relates to a method and a structure of a flash memory. More particularly, the present invention relates to a self-aligned fabricating process and a structure of a source line of an ETOX memory.
2. Description of the Related Art
ETOX flash memory is a type of conventional erasable programmable read only memory (EPROM) that also incorporates a thin tunnel oxide structure. In fact, ETOX is the acronym for EPROM with tunnel oxide.
FIG. 1 is a schematic top view showing a portion off an ETOX flash memory unit. FIG. 2A is a schematic, cross-sectional side view taken along line A-Axe2x80x2 in the central region II of FIG. 1. FIG. 2B is another schematic, cross-sectional view along line B-Bxe2x80x2 in the same central region II of FIG. 1. As shown in FIGS. 1, 2A and 2B, the ETOX memory structure is formed by forming a field oxide (FOX) layer 110 in a silicon substrate 100 with the field oxide layer 110 serving as a device isolation structure. A tunnel oxide layer 120, a floating gate 130, an oxide/nitride/oxide (ONO) composite dielectric layer 140 and a control gate 150 are sequentially formed over the silicon substrate 100. The floating gate 130, the ONO dielectric layer 140 and the control gate 150 together constitute a stacked gate. An ion implantation is carried out, implanting ions into the substrate 100 on each side of the stacked gate to form a source line 160 and a drain terminal 170. Bit line contact 180 is also formed in the drain 170 region so that bit line (not shown in the figure) running over the stacked gate can be electrically connected to the drain 170. The bit line runs in a direction parallel to the field oxide layer 110, and is therefore perpendicular to the stacked gate. The source line 160 runs in a direction perpendicular to the field oxide layer 110, and is therefore parallel to the stacked gate.
During the fabrication of an ETOX memory unit, the polysilicon is first deposited over the substrate 100 and then patterned to form a first polysilicon layer 130a as shown in FIG. 3. An ONO dielectric layer 140 is formed over the surface of the first polysilicon layer 130a. A second polysilicon layer is next formed over the silicon substrate 100, and then a self-aligned etching operation is conducted to pattern the second polysilicon layer, the ONO dielectric layer 140 and the first polysilicon layer 130a. Hence, a stacked gate consisting of the floating gate 130, the ONO dielectric layer 140 and the control gate 150 as shown in FIGS. 1, 2A and 2B is formed.
In the self-aligned etching process, the area 190a on the silicon substrate 100 is only covered by a layer of polysilicon (a second polysilicon layer). Therefore, after etching the second polysilicon layer, the ONO dielectric layer 140 and the first polysilicon layer 130a, an opening 190 (shown in FIG. 1) is also formed in area 190a of the silicon substrate 100.
FIGS. 4A and 4B are schematic, cross-sectional views along line IV-IVxe2x80x2 of FIG. 1. After the self-aligned etching process as shown in FIG. 4A, ions from an ion source 200 are implanted into the source line 160 region to form an ion-doped region 210 as shown in FIG. 4B. Since ions are generally implanted in a direction perpendicular to the silicon substrate 100, a very thin ion-doped layer 210a is formed next to the sidewalls of the opening 190. Consequently, discontinuity and high resistance may occur somewhere along the source line 160.
A number of problems may occur if the source line 160 has a high electrical resistance. Operating speed of an ETOX memory cell may decrease. Resistance of the source line 160 can be lowered by either increasing the line width w (as shown in FIG. 1) or increasing the concentration of ion dopants inside the source line 160. However, increasing the width w of the source line 160 will lower the level of integration. On the other hand, increasing dopant concentration will increase band-to-band tunneling current leading an intensification of current leak problems. In addition, when resistance of the source line 160 is high, a source line contact (not shown in the figure) for every 32 memory bits is essential, thereby lowering the level of integration for ETOX flash memory even further.
A related problem is that field oxide near the bird""s beak area is rather thin. Hence, according to the design rule, a distance must be set aside between the xe2x80x98closexe2x80x99 state stacked gate from the edge of the field oxide layer 110 to prevent current leak. However, by designating a minimum distance of separation, ultimate level of integration for the ETOX flash memory is further reduced.
The invention provides a self-aligned process for fabricating ETOX flash memory. A plurality of parallel lines for device isolation is formed in a substrate, and then a plurality of parallel stacked gates perpendicular to the isolation lines is formed.
A plurality of first insulation layers is formed with an insulation layer above each stacked gate. Spacers are formed over the sidewalls of each stacked gate. At least one source line array is formed in the substrate running parallel to the stacked gates and located between neighboring stacked gates. This source line array comprises a plurality of source-doped regions between the device isolation lines. A second insulation layer is formed over the substrate, and then a line opening is formed in the second insulation layer to expose the device isolation line and the source-doped region cross-over by the source line array. A source line is finally formed inside the opening.
The invention also provides a source line structure for ETOX flash memory. The structure comprises a substrate, a plurality of parallel device isolation lines in the substrate, a plurality of parallel stacked gates perpendicular to the device isolation lines over the substrate, a plurality of first insulation layers, one over each of the stacked gate, and a plurality of spacers on the sidewalls of the stacked gates. In addition, there is a plurality of source line arrays and drain line arrays in the substrate running parallel to the stacked gates and formed between two neighboring stacked gates. The source arrays and the drain arrays alternate in the area between the stacked gates, and each source array comprises a plurality of source-doped regions positioned between the device isolation lines. Similarly, each drain array comprises a plurality of drain-doped regions positioned between the device isolation lines. Furthermore, a plurality of source lines is formed between neighboring spacers above the source arrays.
According to the self-aligned process of this invention, the source line is dissected by the device isolation line after the substrate doping operation. However, the source line formed above the source array is capable of linking all the individual source-doped regions back together. In addition, resistance of source lines can be lowered by selecting a material having a low resistance such as polysilicon or metal silicide to form the source lines. Hence, concentration of ionic dopants inside the source-doped region can be determined by actual needs instead of considerations concerning source line resistance. Moreover, a low source line resistance permits the reduction of the area required to form source line contact. On the other hand, the linking together of the device isolation structures is capable of reducing the minimal safety distance between the stacked gate and the edge of the device isolation structure. In brief, the invention not only can lower source line resistance leading to an increase in operating speed, but also can increase the level of integration of the flash memory considerably.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.